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MU9C4K64-12TDC Datasheet PDF - Music Semiconductors

Part Name
Description
MFG CO.
MU9C4K64-12TDC
Music-Semiconductors
Music Semiconductors Music-Semiconductors
Other PDF
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MU9C4K64-12TDC Datasheet PDF : PDF DOWNLOAD     
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GENERAL DESCRIPTION
The MU9C RCP family consists of 4K and 8K x 64-bit Routing Coprocessors (RCPs) with a 32-bit wide data interface. The device is designed for use in layer 2 switches to provide very high throughput address translation using tables held in external RAM. The MU9C RCP has a fully deterministic search time, independent of the size of the list and the position of the data in the list. This unique feature guarantees that the wire speed address recognition does not impact the latency or induce some jitter on the latency of the global system. Address fields from the packet header are compared against a list of entries stored in the array. As a result of the comparison, the MU9C RCP generates an index that is used to access an external RAM where port mapping data and other associated information is stored.

DISTINCTIVE CHARACTERISTICS
• 4K and 8K x 64-bit words
• 64-bit binary compares
• 35 ns deterministic compare and output time
• 32-bit Data I/O port
• 16-bit Match Address Output port
• Address/Control bus directly controls device operations for
   faster operation or higher throughput
• Seven selectable mask registers
• Synchronous operation
• Cascadable for increased depth
• Extensive set of control states for flexibility
• JTAG interface
• 100-pin LQFP package; 3.3 Volt operation

APPLICATION BENEFITS
• 28 million IPv4 packets per second supports up to 18
   Gb Ethernet or 7 OC-48 ATM ports at wire speed
• Exact match on MAC addresses
• Processes DA and SA within 190 ns, supporting three ports
   of 1 Gb or 34 ports of 100 Mb Ethernet at wire
   speed
• Mixed mode L3 and L2 single search engine for two ports
   at 1 Gb or 29 ports of 100 Mb Ethernet at wire
   speed
• Directly addresses external RAM containing
   associated data of any width
• Hardware control states directly address memory and
   registers; Instruction and Status registers for optional
   software control

 

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